1. Field of the Invention
This invention relates to a method of forming fine conductive lines, patterns and connectors. The method is particularly useful for the formation of electronic devices.
2. Background Art
The production of micron and submicron dimension electronic devices requires high accuracy in forming fine conductive lines, patterns and connectors. These fine lines and patterns may be part of an individual electronic device structure or may be connecting lines between numerous electronic devices contained within one overall structure or package.
One of the best known and most frequently used techniques for producing fine conductive lines and patterns is the lift-off process. In the lift-off process, a substrate is coated with a polymeric radiation-sensitive layer (resist layer), the upper surface of which is subsequently irradiated to create a pattern of differential solubility or etch resistance within the layer. The desired pattern can be developed either by exposing the irradiated resist layer to a solvent capable of dissolving the irradiated portion (positive-tone resist) or the non-irradiated portion (negative-tone resist). Another technique of developing a resist is to react the irradiated resist with an organometallic reagent which reacts in the irradiated areas of the resist, and then expose the resist layer to an etchant, such as an oxygen plasma, which removes the less etch-resistant, non-irradiated portions of the resist layer. After formation of the patterned resist layer, a conductive layer is applied over the surface of the patterned resist, so that the conductive material fills the openings in the patterned resist layer, contacting the substrate beneath. Subsequently, the conductive material on the upper surface of the patterned resist is removed by treating the polymeric resist thermally or with a solvent, so the polymeric material vaporizes or dissolves away, simultaneously lifting-off overlaying conductive material. The portion of conductive material which filled the openings in the patterned resist layer is left upon the substrate. The lift-off process suffers the disadvantage that frequently portions of the conductive material filling the openings in the patterned resist are removed along with the conductive material overlaying the patterned resist; thus, imperfect lines or patterns remain, sometimes to the extent of creating an open along a conductive line so the electronic device cannot function.
Recently, techniques have been developed for the chemical-mechanical polishing of semiconductor wafers which permit a high degree of accuracy in the uniformity of polished wafer flatness. The description of such a process is presented in detail in U.S. Pat. No. 4,450,652 to R. J. Walsh. In addition, use of chemical-mechanical polishing to enhance removal of non-planar regions of a surface by chemically reacting portions of the surface while mechanically applying force to the chemically reacting portions is described in U.S. Pat. No. 4,435,247 to Basi et al.
It would be advantageous to the microelectronics industry to have a method of producing fine conductive lines by a more reliable and cost effective technique than the current lift-off technology. In addition, it would be desirable to have a simplified process for forming a structure comprising a polymeric insulator in which conductive features, such as fine lines and connectors (horizontal and vertical), are isolated from other conductive features.